NAG and Intel 2 Day Training Course

Improving Application Performance on the Intel Xeon Phi Processor

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Location: Rice University, Houston, TX

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Date: April 25-26, 2017

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Course Introduction

This two-day course teaches the fundamental skills needed to achieve optimum performance on the Intel® Xeon Phi™ Processor.

NAG HPC Engineers will show how to gain application performance gains on the Intel Xeon Phi Processor through the use of OpenMP; this entails fully utilizing all cores as well as efficient use of its SIMD vectorization capabilities.

The course features practical ‘hands-on’ sessions to fully illustrate each key topic. This is a 'Bring Your Own Laptop' training course. Individuals are very welcome to attend without a laptop to enjoy the technical lectures and training, but will not be able to participate in the practical exercises.

Day 1

Day 1 covers the Intel Xeon Phi Processor and teaches how to use OpenMP to introduce parallelism. OpenMP also enables vectorization capabilities, and participants will learn to use this feature effectively for the new AVX-512 vectorization capabilities available in the Intel Xeon Phi Processor. This ends with a practical exercise taking a real-world code that is not parallelized or vectorized and using OpenMP to achieve these two things for significant performance gains.

Day 2

Day 2 focuses on optimizing the Intel Xeon Phi Processor resource utilization for already-parallel codes. Here we take an existing parallel code and further optimize data locality, data layout, thread affinity. We demonstrate the use of Intel VTune to identify when an application can benefit from these optimizations.

Results

By the end of this course, attendees will know the Intel Xeon Phi Processor and what applications can best leverage it.

They will also know how to use OpenMP to utilize multicore parallelism as well as vectorization, and they will know how to further optimize already-parallel applications to even more efficiently utilize the Intel Xeon Phi Processor and maximize performance.

Equipped with this knowledge, attendees will be able to take an initial application and optimize it for excellent performance on the Intel Xeon Phi Processor.

SCHEDULE

Day 1

09.00 Registration
09.30 Intel Introduction
09.45 Lecture 1 - Introduction to the Intel Xeon Phi Processor
10.30 Break
10.45 Exercise 1 - Compiling and Running on the Intel Xeon Phi Processor
11.15 Lecture 2 - Introduction to Parallel programming using OpenMP
12.00 Lunch
13.00 Exercise 2 - Using OpenMP Directives for Parallelization
15.00 Break
15.15 Lecture 3 - OpenMP Optimization
16.00 End of Day 1

Day 2

09.00 Questions and Discussion from Day 1
09.15 Lecture 4 - Vectorization
10.00 Exercise 3 - Enabling Vectorization and other Optimizations
10.30 Break
10.45 Continue Exercise 3
12.00 Lunch
13.00 Lecture 5 - Intel Xeon Phi Processor Specific Optimizations
14.00 Exercise 4 - Intel Xeon Phi Processor Optimizations
14.30 Break
14.45 Finish Exercise 4
15.30 Our Parallel Programming Pearls, Summarize
16.00 End of Course

Access to Intel Xeon Phi Processors for training material development and lab exercises is provided by the Texas Advanced Computing Center at the University of Texas, Austin.